William RickertandClaude Opus 5
49ad7e97cf
Parsed the pin-definition tables out of both datasheets - Table 2-1-1 (CH32L103, C8T6 column) and Table 2 (STM32F103, LQFP48 column) - and diffed them pin by pin. Zero mismatches, including OSC_IN/OSC_OUT, NRST, PA11/PA12 for USB, PA13/PA14 for SWD, and BOOT0. Power pins differ only in naming. This was the one unverified assumption the whole project rested on: three boards laid out to a footprint that has to accept either MCU. It holds. Full table recorded in Documents/pinout-L103-vs-F103.md. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
61 lines
2.3 KiB
Markdown
61 lines
2.3 KiB
Markdown
# CH32L103C8T6 vs STM32F103C8T6 — LQFP-48 pin overlay
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**Result: all 48 pins identical. Zero mismatches.**
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Verified 2026-09-01 by parsing the pin-definition tables out of both datasheets
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in `Documents/` — Table 2-1-1 (CH32L103, C8T6 column) and Table 2 (STM32F103,
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LQFP48 column) — and diffing them pin by pin. This is the assumption the whole
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project rests on: the boards are laid out to this footprint so either MCU can be
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populated.
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Every pin below carries the same signal on both parts.
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| # | Signal | | # | Signal | |
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|---|---|---|---|---|---|
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| 1 | `VBAT` | | 25 | `PB12` | |
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| 2 | `PC13` | | 26 | `PB13` | |
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| 3 | `PC14` | | 27 | `PB14` | |
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| 4 | `PC15` | | 28 | `PB15` | |
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| 5 | `OSC_IN` | crystal | 29 | `PA8` | |
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| 6 | `OSC_OUT` | crystal | 30 | `PA9` | |
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| 7 | `NRST` | reset | 31 | `PA10` | |
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| 8 | `VSSA` | | 32 | `PA11` | USB D− |
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| 9 | `VDDA` | | 33 | `PA12` | USB D+ |
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| 10 | `PA0` | | 34 | `PA13` | SWDIO |
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| 11 | `PA1` | | 35 | `VSS_2` | |
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| 12 | `PA2` | | 36 | `VDD_2` | |
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| 13 | `PA3` | | 37 | `PA14` | SWCLK |
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| 14 | `PA4` | | 38 | `PA15` | |
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| 15 | `PA5` | | 39 | `PB3` | |
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| 16 | `PA6` | | 40 | `PB4` | |
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| 17 | `PA7` | | 41 | `PB5` | |
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| 18 | `PB0` | | 42 | `PB6` | |
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| 19 | `PB1` | | 43 | `PB7` | |
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| 20 | `PB2` | BOOT1 | 44 | `BOOT0` | BOOT0 |
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| 21 | `PB10` | | 45 | `PB8` | |
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| 22 | `PB11` | | 46 | `PB9` | |
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| 23 | `VSS_1` | | 47 | `VSS_3` | |
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| 24 | `VDD_1` | | 48 | `VDD_3` | |
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## The nine that actually matter
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| Pin | Signal | Why |
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|---|---|---|
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| 5 / 6 | `OSC_IN` / `OSC_OUT` | 8 MHz crystal — both parts, same pins |
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| 7 | `NRST` | reset |
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| 20 | `PB2` | BOOT1 |
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| 32 / 33 | `PA11` / `PA12` | USB D− / D+ |
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| 34 / 37 | `PA13` / `PA14` | SWDIO / SWCLK |
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| 44 | `BOOT0` | boot select |
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## Caveats
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- Power pins differ only in **naming**: the L103 labels them `VSS`/`VDD`, the
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F103 numbers them `VSS_1..3`/`VDD_1..3`. Same pins, same function.
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- The F103 datasheet used is **Rev 1 (preliminary)** — see `Documents/README.md`.
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A released package's pinout does not change between datasheet revisions
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(it would break every existing design), so this is sound. If you want
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belt-and-braces, spot-check pins 32/33/34/37 against the current Rev 20.
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- This verifies **pin assignment only**. Electrical differences remain — most
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importantly `R5`, the 1.5 kΩ D+ pull-up the F103 needs and the L103 doesn't.
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